Edvardsson, Adam

sd card controller

This file could not be downloaded.
please repair it.

Untitled bug

The check bits of R2 response should be 2'b111111 and the CRC7 should not protect these bits.

The following code should be inserted between lines 657 and 658 of the "sdModel.v"

        if (response_S == 136)
            crcEn<=(cmdWrite >= 6);

and line 466 of "sd_cmd_serial_host" shoud be updated as

        CRC_Enable=(Response_Size <= 40 || Cmd_Cnt > 7);

to fix this problem.

Incorrect R2 Response

Multiple block transfers via dma would be very useful. I am not able to attain better than ~1.5MB/s using the single block read. Multiple block writes are even more important because of pre erase.

Multiple block transfers

Would it be possible to release a version of this core integrated into Altera's Quartus & Nios environment?

The core as is do not compile with Quartus. With few modification i got it to compile and integrate with NIOS (WB Slave only for now), but unfortunately it does not work yet. Not sure if my modifications is causing the problem now?

Thanks

Altera / Nios compatible version

Hi Edward, project file for download doesn't correnspond to svn files, can you update this ? Thanks a lot

project dowload

I think the current simulation, defines are for the DMA mode.
For PIO mode, what files, defines should be included/exclluded?
Thanks

PIO mode

Hi,

I am interested in Joining with you for designing V.2

Design without Buffer descriptors

Hi,
   I would like to re-design SD-Controller with following modifications, 
(1) Design without Buffer descriptors. Lets use CMD17,CMD24 from s/w to send 
    SD Card sector address.
(2) If we implement first step, then we need to change Data master.
(3) Instead of using SD External memory, I would like to write/read from CPU.
    To CPU can read/write only from a 32bit register. Data for load/store will
    be taken from the 32bit register.

Could you please suggest needed modifications for the uploaded design.

Browse

sd card controller