sd card controller
Hi, I would like to re-design SD-Controller with following modifications, (1) Design without Buffer descriptors. Lets use CMD17,CMD24 from s/w to send SD Card sector address. (2) If we implement first step, then we need to change Data master. (3) Instead of using SD External memory, I would like to write/read from CPU. To CPU can read/write only from a 32bit register. Data for load/store will be taken from the 32bit register.
Could you please suggest needed modifications for the uploaded design.
Hello. Thanks for the suggestions.
(1)I have been thinking on redesigning this as well.
Because Im currently writing Linux drivers to the Controller and noticed that the middle layer want to send CMD18 and CMD25. (Multiple Block operations)
Change this and we will get a controller with more performance and in more standardized way. Also today there is no support to get the Wide data registers
(2) The Redesign will involve something like :. 1. Remove BD, just 1 Memory Source register needed. 2. No Internal generation of command in Data_Master 3. Data_Serial Host has to know when multiple I/O operations is running. 4. Data_Serial_Host most detect stop command 5. Data_Serial_Host most know size of incoming data.
(3) You want a mode where the CPU takes care of filling the buffer?
Also today there is no support to get the Wide data registers. That can be easily updated with a little bit of modification in READ_WR state of DATA_SERIAL_HOST module.(with four response registers each of 32bit)
Few more points:- I think clock control like bypassing and clock division is hard-coded in current design.We can add a clock control register.We can even add a data control register, which indicates the block size, direction, data-path enabling etc...
(3) You want a mode where the CPU takes care of filling the buffer? -->Exactly. Peripheral I/O based IP with DMA & Non-DMA modes of operation.
Clock divider register is implemented and can be changed during runtime from SW, however the clock divider is not a very good one, the clock divisons occures in to big step.
A dynamic changable block-size and data width would also be more inline with normal SD controllers.
Yes i guess PIO mode would be useful when using the controller on system without OS.
The FIFO should now be made of block-RAM instead when the buffer descriptor isn't needed.
Seems like you have good knowledge of the Core Thinking about creating a new V.2 SD controller project, if u wanna join i would be grateful.
Hi, i am trying to get the sd core working on Altera and compiling it with Quartus V9.1 SP2 I had to make few small changes to the verilog for a successful compilation in Quartus. I connected the Slave WB to NIOS (Master WB left open for now) and can read and write registers successful. However, when i start with initialization part of your software example e.g. clk divider reg ext as soos as i write 0x00 to CMD and ARG (e.g. SD Reset) i get successful reponse, but the CMD line starts to loop. It looks like valid data but keeps on triggering the ossiloscope. When CMD8 is issued after SD Reset (supported only in V2.0) i get no respone => no V2.0 compatible card. But this is not true. The Card is V2.0 & all hardware is proven.
Any ideas where i can start to test what is going on? I would like to write and read a single register on the SD Card first to test that interface.
When will V2.0 of the core be released. I see in the posts that you were thinking of making a few changes?
Would it be possible to release a Altera/NIOS version as well? This would be widely used.
Much appreciated Thanks!!
Sorry i posted my remarks at the wrong place, except for the question on the release of V2.0