Edvardsson, Adam

sd card controller

Simulation doesn't work, straight out of the box.

access_to_reg TEST
  Time: 925
  TEST 0: 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )
  Time: 1005
Wrong defaulte value @ addr d0000058, tmp_data xxxxxxxx, should b 00000000
  Time: 1161
Register could not be written to FFFF_FFFF - addr d0000058, tmp_data 00000000
  Time: 1239
Wrong defaulte value @ addr d0000004, tmp_data 000000ff, should b 00000000
  Time: 1395
Register could not be written to FFFF_FFFF - addr d0000004, tmp_data 00000000
... lots more ...

Sim broken

I totally remade it. 20-30 mistakes..   wrong edges, fake simulation delays. now it works fine on xilinx

I raised it

This file could not be downloaded.
please repair it.

Untitled bug

The check bits of R2 response should be 2'b111111 and the CRC7 should not protect these bits.

The following code should be inserted between lines 657 and 658 of the "sdModel.v"

        if (response_S == 136)
            crcEn<=(cmdWrite >= 6);

and line 466 of "sd_cmd_serial_host" shoud be updated as

        CRC_Enable=(Response_Size <= 40 || Cmd_Cnt > 7);

to fix this problem.

Incorrect R2 Response

Multiple block transfers via dma would be very useful. I am not able to attain better than ~1.5MB/s using the single block read. Multiple block writes are even more important because of pre erase.

Multiple block transfers

Would it be possible to release a version of this core integrated into Altera's Quartus & Nios environment?

The core as is do not compile with Quartus. With few modification i got it to compile and integrate with NIOS (WB Slave only for now), but unfortunately it does not work yet. Not sure if my modifications is causing the problem now?

Thanks

Altera / Nios compatible version

Hi Edward, project file for download doesn't correnspond to svn files, can you update this ? Thanks a lot

project dowload

Hi, 

I tried to run the testbench provided in the deliverable. However, it appears that the wishbone READ was not successful, with the ModelSim output attached below. It would be great to have some documentation on the testbench, as I found it fairly hard to figure out what went wrong in the testbench if the simulation prints out error messages. 

#  
# access_to_reg TEST
#   Time: 13405
#   TEST 3.0: 0:  Init Seq, No Response  
# *W, cycle already in progress when start_cycle routine was called! Time                13000 
# *W, cycle already in progress when start_cycle routine was called! Time                14000 
# *W, cycle already in progress when start_cycle routine was called! Time                14000 
# *W, cycle already in progress when start_cycle routine was called! Time                14000 
# *W, cycle already in progress when start_cycle routine was called! Time                14000 
# *W, cycle already in progress when start_cycle routine was called! Time                14000 
# *E, wb_block_read routine re-entered! Time                14000 
#   Time: 14005
# *E WISHBONE Master was unable to complete the requested read operation from MAC!
# *W, cycle already in progress when start_cycle routine was called! Time                14000 
# *W, end_cycle routine called when CYC_O value was 0! Time                14000 
# *E, wb_block_read routine re-entered! Time                19000 
#   Time: 19179
# *E WISHBONE Master was unable to complete the requested read operation from MAC!
# *W, cycle already in progress when start_cycle routine was called! Time                19000 
# *W, cycle already in progress when start_cycle routine was called! Time                19000 
# *E, wb_block_read routine re-entered! Time                19000 
#   Time: 19387
# *E WISHBONE Master was unable to complete the requested read operation from MAC!
# *W, cycle already in progress when start_cycle routine was called! Time                19000 
# *W, cycle already in progress when start_cycle routine was called! Time                20000 
# *E, wb_block_read routine re-entered! Time                20000 
#   Time: 19595
# *E WISHBONE Master was unable to complete the requested read operation from MAC!
# *E, wb_block_read routine re-entered! Time                20000 
#   Time: 19621
# *E WISHBONE Master was unable to complete the requested read operation from MAC!
# *W, cycle already in progress when start_cycle routine was called! Time                20000 
# *W, cycle already in progress when start_cycle routine was called! Time                20000 
# *E, wb_block_read routine re-entered! Time                20000 
#   Time: 19855
# *E WISHBONE Master was unable to complete the requested read operation from MAC!
# *E, wb_block_read routine re-entered! Time                20000 
#   Time: 19881
# *E WISHBONE Master was unable to complete the requested read operation from MAC!
# CID reg 1: xxxxxxxx
# *W, cycle already in progress when start_cycle routine was called! Time                20000 
# *W, cycle already in progress when start_cycle routine was called! Time                20000 
# *E, wb_block_read routine re-entered! Time                20000 
#   Time: 20115
# *E WISHBONE Master was unable to complete the requested read operation from MAC!
# *E, wb_block_read routine re-entered! Time                20000 
#   Time: 20141
# *E WISHBONE Master was unable to complete the requested read operation from MAC!
# RCA Response: xxxxxxxx
# RCA Nr for data transfer: 0000xxxx
# 
# ===========================================================================
# T2 test_init_sequence Completed
# ===========================================================================

clarification of testbench

Greetings!

We try to compile this project in the QuartusII environment. Compilation was failed. 
Uncommenting DEFINE ALTERA @ commenting DEFINE ACTEL in the SD_DEFINES.V file takes no effect.
What we must change in this project to use FPGA Altera?

Thank You!

Using FPGA Altera

Greetings!

We try to compile this project in QuartusII with errors.
Uncommenting DEFINE ALTERA and commenting DEFINE ACTEL In the SD_Defines.v file takes no effect.
What we must change in this project for Altera using?

ThankYou!

I think the current simulation, defines are for the DMA mode.
For PIO mode, what files, defines should be included/exclluded?
Thanks

PIO mode

In wb_slave_behavioral.v, the test data file wb_memory.txt is missing, can you upload? Thanks.

Missing file: wb_memory.txt

At the time of SD data reading, an FIFO error occurs when define SIM.
This cause is because Wishbone Master Write and Read occurred at the same time.
The point of the problem:
---SD_data_master.v, line:418-419---
rec_done<=1;
start_tx_fifo<=1;

---Modify, line:418-419---
rec_done<=1;
if(!rx_cycle)   <---Add
start_tx_fifo<=1;

On "2: Send CMD3, 48-bit Response, All Error check enable" test, a CRC error occurs and does a loop in a "while" sentence(line 2471).
The point of the problem:
---SD_controller_top_tb.v, line:2364~2365---
sdModelTB0.add_wrong_cmd_crc<=1;
sdModelTB0.add_wrong_cmd_indx<=1;

---Add, line:2442---
sdModelTB0.add_wrong_cmd_crc<=0;
sdModelTB0.add_wrong_cmd_indx<=0;

Testbench (Revision 125)

Hi,

I am interested in Joining with you for designing V.2

Design without Buffer descriptors

Hi,
   I would like to re-design SD-Controller with following modifications, 
(1) Design without Buffer descriptors. Lets use CMD17,CMD24 from s/w to send 
    SD Card sector address.
(2) If we implement first step, then we need to change Data master.
(3) Instead of using SD External memory, I would like to write/read from CPU.
    To CPU can read/write only from a 32bit register. Data for load/store will
    be taken from the 32bit register.

Could you please suggest needed modifications for the uploaded design.

support? RAM_MEM_WIDTH_32

the simulation script refers to plenty of files that are not in the SVN :(

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sd card controller