sd card controller

Greetings!

We try to compile this project in the QuartusII environment. Compilation was failed. Uncommenting DEFINE ALTERA @ commenting DEFINE ACTEL in the SD_DEFINES.V file takes no effect. What we must change in this project to use FPGA Altera?

Thank You!

I think i know onething that might casue problem in altera device.

Remove the GO_IDLE signal in the sd_cm_serial_host.

ROW 4: module SD_CMD_SERIAL_HOST ( SD_CLK_IN, RST_IN, SETTING_IN,GO_IDLE ,CMD_IN, REQ_IN, ACK_OUT, REQ_OUT,ACK_IN, CMD_OUT, STATUS, cmd_dat_i, cmd_out_o, cmd_oe_o, st_dat_t);

module SD_CMD_SERIAL_HOST ( SD_CLK_IN, RST_IN, SETTING_IN,CMD_IN, REQ_IN, ACK_OUT, REQ_OUT,ACK_IN, CMD_OUT, STATUS, cmd_dat_i, cmd_out_o, cmd_oe_o, st_dat_t);

ROW 200: always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE) always @ (posedge SD_CLK_IN or posedge RST_IN )

ROW 202: if (RST_IN || GO_IDLE) begin if (RST_IN ) begin

ROW 213: always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE) always @ (posedge SD_CLK_IN or posedge RST_IN)

ROW 216: if (RST_IN || GO_IDLE) begin if (RST_IN) begin

ROW 234: always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE ) always @ (posedge SD_CLK_IN or posedge RST_IN )

ROW 236: if (RST_IN || GO_IDLE ) begin if (RST_IN ) begin

ROW 283: always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE ) always @ (posedge SD_CLK_IN or posedge RST_IN )

ROW 288-290: else if (GO_IDLE) begin state <= #1 IDLE; end Remove

297: always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE ) always @ (posedge SD_CLK_IN or posedge RST_IN )

299: if (RST_IN || GO_IDLE ) begin if (RST_IN ) begin

317-318: if(GO_IDLE) begin cmd_oe_o=0;

Remove

Then in the sd_controller_top row 255 where the SD_CMD_SERIAL_HOST instantiates, change the .RST_IN from .RST_IN (wb_rst_i | software_reset_reg0), -> .RST_IN (wb_rst_i | software_reset_reg0 | go_idle),

Second change in this module is to remove the GO_IDLE port from the instansation row 257