To get the simulation up and running
If using modelsim:
1. Download the core
2. Enter the "\sim\rtl_sim\run" directory and run the comp.do script.
3. Let the simulation finnish, if succesfull you should get the printout: "# All Tests past"
Synthesise the core
1. Make appropriate changes to SD_Defines.v.
a. The SYN should be defined for synthesize
b. Define you technology (Currently only some specific Actel primitives is in use)
c. Define if you are going to use the bus clock as clocksignal for the SDCard or if an external clock will be used
d. Define if you are going to use the dynamic clock divider or use a static.
e. Define the Block size of you SD Data block
f. Define how widh you SD data bus is
g. Define the size of FIFO