8/16/32 bit SDRAM Controller

there is a port named 'wb_cti_i' which is not in specification datasheet. and my wish bone bus has not this port.... I want to know how to set this.

Currently Design does not uses wb_cti signal. You can tie it to zero. But we may use this signal for feature version.

As the the Wish bone spec, input 2:0 wb_cti_i ; /*** The Cycle Type Idenfier CTI_IO() Address Tag provides additional information about the current cycle. The MASTER sends this information to the SLAVE. The SLAVE can use this information to prepare the response for the next cycle. Table 4-2 Cycle Type Identifiers CTI_O(2:0) Description ‘000’ Classic cycle. ‘001’ Constant address burst cycle ‘010’ Incrementing burst cycle ‘011’ Reserved ‘100’ Reserved ‘101 Reserved ‘110’ Reserved ‘111’ End-of-Burst ****/

-Dinesh Annayya

You can also refer the Test Bench top-level file:

trunk/verif/tb/tb_top.sv to understand the sdrc_top module instantiation.

-Dinesh Annayya