8/16/32 bit SDRAM Controller

I think there is a bug in IP core,if you want to use the SDRAM frequently, your write request and read request may be failed without any alarm from the IP core, for example you want to read a packet, the ip core give you read valid but the data bus is invalid. it is because in some situations IP core don't activate the SDRAM row and command a write or a read without activation so the SDRAM ignore the commands.if you request during the refreshing of the SDRAM I mean when "mgmt st" is one the IP core may forget to issue an activate command before read or write, you can check the rfsh_timer in your code before issuing read or write command to check if this is refresh time or not. in this way you can avoid such conflicts.

Do you failures in FPGA base setup. This IP is used in Silicon and not heard of specific issue .. Let me know if you have specific test case .. I can cross-check