SDRAM Controller with intelligent bank manage
Project maintainers
Details
Name: sdram_controller_wibm
Created: Oct 8, 2026
Updated: Oct 9, 2026
SVN: No files checked in
Bugs: 0 reported / 0 solved
Created: Oct 8, 2026
Updated: Oct 9, 2026
SVN: No files checked in
Bugs: 0 reported / 0 solved
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Other project properties
Category:Memory core
Language:Verilog
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: GPL
Language:Verilog
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: GPL
Description
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The url of the svn repository is: https://opencores.org/websvn/listing/sdram_controller_wibm/sdram_controller_wibm
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