Unsigned serial divider

There is something different in VHDl and Verilog implementation. when I try both in simulator results were different in cases when M_PP and N_PP were different. I thing in Verilog is mistake. When I change line 176: grand_divisor <= divisor_i << (N_PP+R_PP-S_PP-1); by grand_divisor <= divisor_i << (M_PP+R_PP-S_PP-1); the result makes sense to me and it is the same like in VHDL implementation.

In detail, I use parameters: parameter M_PP = 12;
parameter N_PP = 8;
parameter R_PP = 0;
parameter S_PP = 0;
parameter COUNT_WIDTH_PP = 5; parameter HELD_OUTPUT_PP = 0;

Some lines of my comment are lost... Here is it: There is something different in VHDl and Verilog implementation. when I try both in simulator results were different in cases when M_PP and N_PP were different. I thing in Verilog is mistake. When I change line 176: grand_divisor <= divisor_i << (N_PP+R_PP-S_PP-1); by grand_divisor <= divisor_i << (M_PP+R_PP-S_PP-1); the result makes sense to me and it is the same like in VHDL implementation.

In detail, I use parameters: parameter M_PP = 12;
parameter N_PP = 8;
parameter R_PP = 0;
parameter S_PP = 0;
parameter COUNT_WIDTH_PP = 5; parameter HELD_OUTPUT_PP = 0;

Again, grrrr... Simply When I change N_PP+R_PP-S_PP-1 on line 176 by M_PP+R_PP-S_PP-1, the result makes sense to me and it is the same like in VHDL implementation.

Thank you! This resolved a problem that I was having where I was getting incorrect results with different values for M_PP and N_PP.

I just ran into the same bug, spent a bunch of time trying to figure out why the divider gave the wrong results, and eventually found this thread. Why isn't this 2015 bug fixed yet? I basic bug like this in a very old core for such a simple design was the last thing I expected would be wrong with my design.