Clayton, John

Unsigned serial divider

There is something different in VHDl and Verilog implementation. when I try both in simulator results were different in cases when M_PP and N_PP were different. I thing in Verilog is mistake. When I change line 176: grand_divisor  <= divisor_i << (N_PP+R_PP-S_PP-1); by grand_divisor  <= divisor_i << (M_PP+R_PP-S_PP-1); the result makes sense to me and it is the same like in VHDL implementation. 

In detail, I use parameters:
parameter M_PP = 12;         
parameter N_PP = 8;          
parameter R_PP = 0;          
parameter S_PP = 0;          
parameter COUNT_WIDTH_PP = 5;
parameter HELD_OUTPUT_PP = 0;

Verilog-bug?

Hi John,
  Thanks for the serial divider routine.  It works very well.  I concur with Harold's findings.  I was experimenting with the routine to reduce the number of XST synthesis warnings I got.  I thought you might be interested in my notes

Thanks,
Bob S.

-----------------------------------------------------
// Include S_PP in width declaration of grand_divisor to reduce synthesis warnings
reg  [M_PP+N_PP+R_PP-S_PP-2:0] grand_divisor;
-----------------------------------------------------
// Include S_PP in width declaration of subtract_node to reduce synthesis warnings
wire [M_PP+N_PP+R_PP-S_PP-1:0] subtract_node; // Subtract node has extra "sign" bit
-----------------------------------------------------
// Include S_PP in width declaration of divisor_node to reduce synthesis warnings
wire [M_PP+N_PP+R_PP-S_PP-2:0]  divisor_node; // Shifted version of grand divisor
-----------------------------------------------------
// Include S_PP in width declaration of quotient_reg to reduce synthesis warnings
reg  [M_PP+R_PP-S_PP-1:0] quotient_reg;    // Used exclusively for the held output

-----------------------------------------------------
// Include S_PP in width declaration of quotient_node to reduce synthesis warnings
wire [M_PP+R_PP-S_PP-1:0]      quotient_node; // Shifted version of quotient
-----------------------------------------------------
// From: assign divisor_node  = {1'b0,grand_divisor[M_PP+N_PP+R_PP-2:1]};
// To:   assign divisor_node  = {1'b0,grand_divisor[M_PP+N_PP+R_PP-S_PP-2:1]};
// From: if (~subtract_node[M_PP+N_PP+R_PP-1]) grand_dividend <= subtract_node;
// To:   if (~subtract_node[M_PP+N_PP+R_PP-S_PP-1]) grand_dividend <= subtract_node;
// From: assign divisor_node  = {1'b0,grand_divisor[M_PP+N_PP+R_PP-2:1]};
// To:   assign divisor_node  = {1'b0,grand_divisor[M_PP+N_PP+R_PP-S_PP-2:1]};

Reduce XST Synthesis Warnings

Hi John,

First off I wanted to say thanks for posting serial_div_uu on Opencores.com.  It's very simple and well documented.

I think I may have found a simple (but fatal) bug/typo on line 176 where it says:

grand_divisor  <= divisor_i << (N_PP+R_PP-S_PP-1);

I think it should say:

grand_divisor  <= divisor_i << (M_PP+R_PP-S_PP-1);

Shouldn't the divisor be shifted by the size of the dividend?  The way it is written the core only works when the dividend size is equal to the divisor size.

Thanks,
    -Joe Howard

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Unsigned serial divider