The serial_divide_uu is a Verilog coded module that performs binary division. It is fully parameterized, and works in a serial fashion. The number of clock cycles required to complete a divide operation is equal to the number of bits in the quotient plus one.
This module has been tested and debugged in actual hardware on a Xilinx XC2S200E FPGA. It was used to divide pulse width by period in a pulse-width-modulation measurement application (ADXL202E 2-axis MEMS accelerometers.)
The widths of the signals are configurable by parameters, as follows:
M_PP = Bit width of the dividend
N_PP = Bit width of the divisor
R_PP = Remainder bits desired
S_PP = Skipped quotient bits
The skipped quotient bits parameter provides a way to prevent the divider from calculating the full M_PP+R_PP output bits, in case some of the leading bits are already known to be zero. This is the case, for example, when dividing two quantities to obtain a result that is a fraction between 0 and 1 (as when measuring PWM signals). In that case the integer portion of the quotient is always zero, and therefore it need not be calculated.
For those who have the luxury of many clock cycles to use up, this module can provide division results of arbitrary precision.
- Fully parameterized Verilog code, tested and debugged
- No testbench
- Calculates roughly one bit of output per clock cycle.
- Parameter "HELD_OUTPUT_PP" allows user to trade off extra flip-flops for the ability to hold the stable output of the previous divide, during the next divide operation.
- Useful for DSP systems.
- Try it out, this module works.
- Code is very well commented, with a description of operation in the header, which suffices for documentation.
- Thanks to David Sala for writing and submitting a VHDL testbench and VHDL version of this code.
David Sala has gracious translated this module into VHDL code, and provided a testbench for it. This should improve this project and make it accessible and useful to more people. Thanks David!