May 7, 2017 | Remove outdated contact | Lieu, Jeff |
Nov 18, 2012 | I've just added a build folder which can enable you to do a real-time evaluation more quickly | Lieu, Jeff |
Nov 15, 2012 | Update description and verification status | Lieu, Jeff |
Nov 14, 2012 | Just separate the CoreClock to TxClock and Rx Clock for Rx Paths and Tx Path because the transceivers give out clocks this way. Just verified transmission with 88E1111 Phy. Looks good. | Lieu, Jeff |
Oct 22, 2012 | Update description | Lieu, Jeff |
Oct 17, 2012 | Update description | Lieu, Jeff |
Oct 16, 2012 | Auto-negotation successfully tested with Marvell 88E1111 using Altera's lvds channel | Lieu, Jeff |
Sep 29, 2012 | Change of license | Lieu, Jeff |
Mar 19, 2012 | Done simulation with Altera GXB, Use Altera as Link partner, tested both SGMII and 1000BaseX mode | Lieu, Jeff |
Feb 24, 2012 | I appreciate any effort to verify with real-time FPGA. Let me know if you need clarification/disccussion for the source code | Lieu, Jeff |
Feb 22, 2012 | Verified 1000BaseX mode with Altera's transceiver | Lieu, Jeff |
Feb 17, 2012 | Testing by simulating with Altera's Transceiver | Lieu, Jeff |