SGMII
Project maintainers
Details
Name: sgmii
Created: Feb 8, 2012
Updated: May 7, 2017
SVN Updated: Nov 18, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Created: Feb 8, 2012
Updated: May 7, 2017
SVN Updated: Nov 18, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star4you like it: star it!
Other project properties
Category:Communication controller
Language:Verilog
Development status:Beta
Additional info:Design done
WishBone compliant: No
WishBone version: n/a
License: GPL
Language:Verilog
Development status:Beta
Additional info:Design done
WishBone compliant: No
WishBone version: n/a
License: GPL
Description
Generic SGMII / 1000X module that can be connected to any transceiver technology.
This core has been verified with 88E1111 Phy
- Autonegotiation
- Rx & Tx in 1000Mbps mode
- Slow bit rate ~ 10Mbps
I don't have adequate tools to verify at full speed.
I appreciate any effort to verify and report bugs.
Everyone is welcome to try this core.
I can be contacted at lieumychuong@gmail.com for other license/support/bring-up issue.
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