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Details

Name: simple_uart
Created: Sep 30, 2005
Updated: Jul 25, 2019
SVN: Check description below for external links
Bugs: 1 reported / 0 solved
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Other project properties

Category:Uncategorized
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License:

Description

This is a simple yet powerful uart core written in Verilog. It contains a harmonic frequency synthesizer for a baud rate generator (effectively a clock multiplier) so it can use just about any clock frequency. It's fairly small (about 83 slices).

Features

- programmable baud rate generator based on harmonic frequency synthesizer
- small size (120 LUTs / 85 slices)

Status

This core has been used for serial uploads / downloads at 38400 baud in a SoC environment on the Spartan3 Starter Board.