SPI Verilog Master and Slave Interface
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Details
Name: spi_verilog_interface
Created: Jun 12, 2025
Updated: Jun 15, 2025
SVN Updated: Jun 17, 2025
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Jun 12, 2025
Updated: Jun 15, 2025
SVN Updated: Jun 17, 2025
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star0you like it: star it!
Other project properties
Category:Communication controller
Language:Verilog
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This project implements a SPI master controller and a SPI slave controller using verilog HDL.
The parameters 1.CPOL & CPHA, 2.BITORDER, 3.DATAWIDTH are configurable for both master and slave controller, while CLKDIV is configurable for master controller to decide the frequency of sclk, and DRVMODE is configurable for slave controller to fit different sysclk and sclk frequency combination.
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