Backtracking Sudoku solver
Project maintainers
Details
Name: sudoku
Created: Sep 4, 2013
Updated: Jun 27, 2015
SVN Updated: Nov 18, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Sep 4, 2013
Updated: Jun 27, 2015
SVN Updated: Nov 18, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!
Other project properties
Category:Other
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: BSD
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: BSD
Description
Simple backtracking 9x9 Sudoku solver written in Verilog. Uses an exact cover algorithm to quickly find a solution with minimal backtracking (C implementation of algorithm provided too).
High wiring complexity due to explicit "neighbor" interconnect (row, column, and 3x3 sub-block) may result in unroutable designs on FPGA families with reduced routing resources.
Working on an Zynq XC702 FPGA.
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