suslik scalar risc cpu
Project maintainers
Details
Name: suslik
Created: Aug 4, 2015
Updated: Jan 19, 2016
SVN Updated: Sep 2, 2016
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 2 reported / 0 solved
Created: Aug 4, 2015
Updated: Jan 19, 2016
SVN Updated: Sep 2, 2016
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 2 reported / 0 solved
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Other project properties
Category:Arithmetic core
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: BSD
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: BSD
Description
Scalar risc cpu of my own architecture which features dynamic branch predictor (1-bit), single cycle load from l1 data cache, 4-way set-associative 16kb code & data cache(separate). It also has compare-and-jump instruction and lacks condition flags.
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