Created: Aug 26, 2014
Updated: Aug 22, 2018
SVN Updated: Jan 4, 2019
Latest version: download
(might take a bit to start...)
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The SystemVerilog Directed Test Bench.
This project contains an exact duplication of the VHDL Test Bench Package parser and usage model. This enables users to create a simple test environment for verification efforts using SV. This also enables scripts that were used on the VHDL system to be reused in a SV environment. (providing the same functionality is coded in the SV environment.)
Current state is Beta, please report any problems to the bug tracking system so I can address issues.
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