Campbell, Ken

SystemVerilog Directed Test Bench

I am not certain this is a bug and could quite probably be a user error as I am not all that familiar with tclsh. I am trying to learn how to use your tool by using one of your example designs which you provide

In Windows 10 I associated the .tcl extension with the tclsh application (I installed tcl/tk from ActiveState as your doc recommended). I double-click on tb_gen.tcl in windows explorer and the tclsh ui pops up.

In the form I select the directory examples/standard/sv as the Working Directory. I set the Output directory to some other location.

In the list of sv files which the tool found under the working directory, I select dut.sv. Then I set the mode to gen_mod and click the Generate button. The progress bar gets to 42% and never gets any further.

While still stuck at 42% I check in the output directory and see the following files have been generated:

dut_if.sv
tb_mod.sv
tb_top.sv

However, the tb_mod.sv has nothing but comments in it, i.e. no actual code.

Can you please help?

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SystemVerilog Directed Test Bench