Javanthieswaran, Madhumangal

synchronous_reset_fifo with testbench

Not a bug but your enable signals are mistakenly named write_enb and read_enb 
Usually signal names ending with letter 'b' or 'n' means the signal is active with a low logic level.
You should rename your enables 'write_en' and  'read_en' instead.

wrong enable signals names

The signals under reset are assigned with tightly coupled value and are not related to PARAMETERS. What's going on if PARAMETER WIDTH is set to 16
?
You are lucky because it is permissive verilog... in VHDL you will be fired!!! 

if (resetn == 1'b0)
     begin

        write_ptr <= 5'b00000;
        read_ptr <= 5'b00000;
        data_out <= 8'b00000000;

tight values in reset

your code uses 3 parameters:

WIDTH = 8;
DEPTH = 16;
POINTER_SIZE = 5;

Technically this is not a bug, but it is really non-optimal and non recommended.
This is because the DEPTH and POINTER_SIZE are not independent. You should define DEPTH from POINTER_SIZE. Something like: 
  parameter DEPTH = (1 << POINTER_SIZE);

By the way, what you name POINTER_SIZE, is more commonly called ADDR_WIDTH.

eliminate non-free parameter

By using the synchronous_reset_fifo and conveying your Bug/Comments/Ideas etc.,
I would be able to keep this design and test bench upto date and bug free.
Thanks,
Mangal

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synchronous_reset_fifo with testbench