SystemVerilog uart16550
Project maintainers
Details
Name: systemverilog-uart16550
Created: Mar 30, 2010
Updated: May 5, 2010
SVN Updated: May 1, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Created: Mar 30, 2010
Updated: May 5, 2010
SVN Updated: May 1, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star1you like it: star it!
Other project properties
Category:Communication controller
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
RS232 Protocol 16550D uart (mostly supported)
- language : systemVerilog IEEE 1800-2005 (Quaruts2-9.1sp1 Support)
- scale : fpga cyclone3 800cell, >50Mhz
- bus : wishbone
-
TODO:
Lin's automotive standards
-> subset of transport layer circuit
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.