Project maintainers


Name: t51
Created: Apr 25, 2002
Updated: Apr 1, 2014
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 3 reported / 0 solved
Star2you like it: star it!

Other project properties

Development status:Stable
Additional info:FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: LGPL


8052 compatible microcontroller core. Two different top levels: T8052: - Single cycle synchronous RAM/ROM - Wishbone bus interface for memory mapped peripherals T8032: - Wishbone bus interface A utility to create VHDL ROMs is also included. To create a ROM compatible with the 8052 core type: hex2rom [-b] inputfile.hex ROM52 13b8s > ROM52.vhd Leonardo Spectrum can infer the ROMs created with hex2rom to Xilinx block RAM. I have also modified the baud rate recognition of the BASIC-52 ROM to support the faster instruction timing. The modified BASIC-52 might also work with other high speed 8032 compatible cores such as the 80c320. Browse source code here. Download latest tarball here.


- All peripherals/interrupts implemented
- Single cycle per byte fetch
- Supports synchronous RAM/ROM
- Single cycle MOVX (8052)
- Optional second DPTR
- Technology independent
- Three stage pipeline