Voggeneder, Andreas

T51 mcu

Hello,

I start to use this MCS51 description but I have some questions:
- What are the differences between the T51s architecture and the T51 one?
- What is the T51s status?
- Is it fully tested?
- If no, what remains to be done?

Currently, I use the T51s architecture and the following instruction does not have any effect on the accumulator content:

mov a, 083h

Thank you in advance

Thoma

T51s purpose

If I get the Wishbone specs right, during a write-cycle, Strobe, Cycle and Write Enable should be asserted (see 3.2.2. SINGLE WRITE cycle). This is not the case when I instantiate the core without any internal XRAM by setting XRAMAddressWidth to zero.

The external Wishbone signals are defined like this:
  XRAM_CYC_O <= ext_ram_en and ram_access;
  XRAM_STB_O <= ext_ram_en and ram_access;
  XRAM_WE_O  <= RAM_Wr;

Tracing ext_ram_en to its driver:
  zeros <= (others => '0');
	g_rams0 : if XRAMAddressWidth > 15 generate
		ext_ram_en <= '0'; -- no external XRAM
	end generate;

	g_rams1 : if XRAMAddressWidth < 16 and  XRAMAddressWidth > 0 generate -- >= ??
		ext_ram_en <= '1' when XRAM_Addr(15 downto XRAMAddressWidth) /= zeros else 
		              '0';
	end generate;

One can see that when XRAM_AddressWidth is zero, ext_ram_en is never driven high. The fix is already in the code above, in form of a comment. So the line in question should be:

	g_rams1 : if XRAMAddressWidth < 16 and  XRAMAddressWidth > =0 generate

While looking at the code, I wondered if XRAM_WE_O should also be qualified with ext_ram_en (and probably ram_access?) like so
  XRAM_WE_O <= ext_ram_en and RAM_Wr;

XRAMAddressWidth=0 prevents write on Wishbone bus

The way this file is currently implemented means there can potentially be 3 active addresses on any one cycle (IntAddrA, IntAddrB and IntAddrA_r). This means an ASIC implementation requires a 3 port RAM, which is clearly less efficient than a dual port.

Is there really any cycle where all three addresses are active?

I dont beleive this is the case. I am guessing IntAddrB is never used during a write cycle (which is the only time IntAddrA_r is used) and therefore these 2 addresses could share the second port.

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T51 mcu