TMS1000
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Details
Name: tms1000
Created: Mar 21, 2021
Updated: Mar 21, 2021
SVN Updated: Mar 22, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Mar 21, 2021
Updated: Mar 21, 2021
SVN Updated: Mar 22, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star0you like it: star it!
Other project properties
Category:Processor
Language:Verilog
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Beta
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This is a Verilog code for TMS1000 4-bit processor chip generally used in calculators.
Modelsim based tcl/tk GUI testbench illustrates the TMS1000 used as
an interval timer and performs integer BCD multiplication, division,
addition, and subtraction. The calculator is described in tms1000 programmers reference
manual. Similarly SR-16 calculator emulation is also done.
The url of the svn repository is: https://opencores.org/websvn/listing/tms1000/tms1000
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