Serial UART

IntRx_N and IntTX_N are generally used to acknowledge end of transmission and to report that new data is available.

However, these signals are assigned inside of an incomplete switch case of StatM, which is built of DRdy, FErr, OErr, TBufE and TRegE. If any of the errors are set, none of the interrupts will be asserted any longer.

Solution: remove the assignments of the interrupts of the switch case, put them together where they are asserted back to 1, by the read and load signals. Besides, the IntTx_N was reporting end of transmission already at the beginning of it, because it was only checking if the data was arrived at the TxUnit. Instead I am checking now for both, buffer empty (data arrived at TxUnit) and register empty (data has been sent).

     case StatM is
          when "00001" =>

•              IntRx_N <= '0';
               CSReg(2) <= '1';
          when "10001" =>

•              IntRx_N <= '0';
               CSReg(2) <= '1';

•         when "01000" =>

•              IntTx_N <= '0';
          when "11000" =>

•              IntTx_N <= '0';
                 CSReg(3) <= '1';
            when others => null;
       end case;

  @@ -164,41 +160,40 @@ if Read = '1' then CSReg(2) <= '0'; IntRx_N <= '1';

•    elsif DRdy = '1' then

•       IntRx_N <= '0';
     end if;

•    if Load = '1' then

•    if LoadTX = '1' then
        CSReg(3) <= '0';
        IntTx_N <= '1';

•    elsif ( TBufE and TRegE ) = '1' then

•       IntTx_N <= '0';           
     end if;
  end if;

  end process;