Created: Sep 25, 2001
Updated: Apr 14, 2010
SVN Updated: May 5, 2009
Latest version: download
(might take a bit to start...)
3 reported / 0 solved
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Other project properties
- as small as possible to fit in a Xilinx CPLD
- fixed 9600 baudrate for this version
- 1 start bit, 8 data bits, 1 stop bit data stream format
- both interrupt-based and polling user interface
Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we needed a way of communication with a host computer, to make it available over the net.
Synthesized with Xilinx Foundation 2.1i (Synopsys Express FPGA compiler, Xilinx P&R tools) for:
- Xilinx Virtex FPGA family takes 14% of XCV50 slices (110 out of 768)
- Xilinx 9500 CPLD family takes 43% of XC95288 macrocells(125 out of 288)
- design is available in VHDL from OpenCores CVS (see Download section)
- documentation will be available in short time
- a new module, UART16550 family compatible could be developed if enough interest
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