Lupas, Ovidiu

Serial UART

Instead of making the process simply sensitive to SysClk, I would register the signals on the rising edge and make Read and Load combinational. 

+  
+  Read <= not (CS_N or RD_N);
+  Load <= not (CS_N or WR_N);
+  
   process(SysClk)
   begin
-     if (CS_N = '0' and RD_N = '0') then
-        Read <= '1';
-     else Read <= '0';
-     end if;
-  
-     if (CS_N = '0' and WR_N = '0') then
-        Load <= '1';
-     else Load <= '0';
-     end if;
+    if Rising_Edge(SysClk) then
+         if (Read = '1' and Addr = "00") then
+            DataOut <= RxData;
+         elsif (Read = '1' and Addr = "01") then
+            DataOut <= CSReg;
+         end if;
 
-     if Read = '0' then
-        DataOut <= "ZZZZZZZZ";
-     elsif (Read = '1' and Addr = "00") then
-        DataOut <= RxData;
-     elsif (Read = '1' and Addr = "01") then
-        DataOut <= CSReg;
-     end if;
-
-     if Load = '0' then
-        TxData <= "ZZZZZZZZ";
-     elsif (Load = '1' and Addr = "00") then
-        TxData <= DataIn;
-     end if;
+         if (Load = '1' and Addr = "00") then
+            TxData <= DataIn;
+            LoadTX <= '1';
+         else
+            LoadTX <= '0';
+         end if;
+    end if;
   end process;

interface process

IntRx_N and IntTX_N are generally used to acknowledge end of transmission and to report that new data is available. 

However, these signals are assigned inside of an incomplete switch case of StatM, which is built of DRdy, FErr, OErr, TBufE and TRegE. If any of the errors are set, none of the interrupts will be asserted any longer. 

Solution:
remove the assignments of the interrupts of the switch case, put them together where they are asserted back to 1, by the read and load signals. Besides, the IntTx_N was reporting end of transmission already at the beginning of it, because it was only checking if the data was arrived at the TxUnit. Instead I am checking now for both, buffer empty (data arrived at TxUnit) and register empty (data has been sent). 

         case StatM is
              when "00001" =>
-                  IntRx_N <= '0';
                   CSReg(2) <= '1';
              when "10001" =>
-                  IntRx_N <= '0';
                   CSReg(2) <= '1';
-             when "01000" =>
-                  IntTx_N <= '0';
              when "11000" =>
-                  IntTx_N <= '0';
                   CSReg(3) <= '1';
              when others => null;
         end case;
@@ -164,41 +160,40 @@
         if Read = '1' then
            CSReg(2) <= '0';
            IntRx_N <= '1';
+        elsif DRdy = '1' then
+           IntRx_N <= '0';
         end if;
 
-        if Load = '1' then
+        if LoadTX = '1' then
            CSReg(3) <= '0';
            IntTx_N <= '1';
+        elsif ( TBufE and TRegE ) = '1' then
+           IntTx_N <= '0';           
         end if;
      end if;
   end process;

IntTx_N and IntRx_N are interdependent and also depend on error signals

Even if the user submits first the data and then drives CS_N and WR_N, the module TX_Unit will not get the right data. 

TxData is assigned 1 clock later than load, and the same load is used by the TxUnit to load the same TxData, which is not available at the moment. 

Solution, create another signal LoadTX, assign it together with TxData, miniUART.vhd:

-     if Load = '0' then
-        TxData <= "ZZZZZZZZ";
-     elsif (Load = '1' and Addr = "00") then
-        TxData <= DataIn;
-     end if;
+         if (Load = '1' and Addr = "00") then
+            TxData <= DataIn;
+            LoadTX <= '1';
+         else
+            LoadTX <= '0';
+         end if;
+    end if;

Besides, I think it might be useful to keep TxData, instead of tri-stating it.

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Serial UART