OpenCores
Issue List
interface process #3
Open rfajardo opened this issue over 14 years ago
rfajardo commented over 14 years ago

Instead of making the process simply sensitive to SysClk, I would register the signals on the rising edge and make Read and Load combinational.

  • Read <= not (CS_N or RD_N);
  • Load <= not (CS_N or WR_N);
  • process(SysClk) begin
  • if (CS_N = '0' and RD_N = '0') then
  •    Read <= '1';
  • else Read <= '0';
  • end if;
  • if (CS_N = '0' and WR_N = '0') then
  •    Load <= '1';
  • else Load <= '0';
  • end if;
  • if Rising_Edge(SysClk) then
  •     if (Read = '1' and Addr = "00") then
  •        DataOut <= RxData;
  •     elsif (Read = '1' and Addr = "01") then
  •        DataOut <= CSReg;
  •     end if;
  • if Read = '0' then
  •    DataOut <= "ZZZZZZZZ";
  • elsif (Read = '1' and Addr = "00") then
  •    DataOut <= RxData;
  • elsif (Read = '1' and Addr = "01") then
  •    DataOut <= CSReg;
  • end if;
  • if Load = '0' then
  •    TxData <= "ZZZZZZZZ";
  • elsif (Load = '1' and Addr = "00") then
  •    TxData <= DataIn;
  • end if;
  •     if (Load = '1' and Addr = "00") then
  •        TxData <= DataIn;
  •        LoadTX <= '1';
  •     else
  •        LoadTX <= '0';
  •     end if;
  • end if; end process;

Assignee
No one
Labels
Idea