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Details

Name: uart6551
Created: Jul 12, 2019
Updated: Aug 3, 2022
SVN Updated: Aug 3, 2022
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Communication controller
Language:Verilog
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

uart6551 is a 6551 register compatible uart core. It is a 32-bit bus peripheral and features 32-bit wide registers with additional functionality. The low order eight bits are compatible with a 6551 uart. Features include 16-byte fifo's and an extended baud rate range. It's possible to specify a clock divisor so that any baud rate may be generated.

uart6551x12 is a 6551 register compatible uart core that supports 12-bit bytes. However, it may be used as an eight-bit peripheral by connecting only the low order eight data lines.

uart6551sbi is an experimental version with a synchronous 8-bit bus interface similar to a 68xx/65xx bus. The registers have been rearranged into 17 8 bit registers. The first four registers function compatibly with a 6551 uart.

The url of the svn repository is: https://opencores.org/websvn/listing/uart6551/uart6551