Uart (FIFO cpu interface) with SV Self-Checking Testbench
News
| Jan 3, 2011 | Added inital version of UART RTL and SV testbench source code. Source and testbench compile without error, but not debugged in the simluator yet. | Bridger, Andrew |
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.