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Details

Name: uart_serial
Created: May 31, 2008
Updated: May 31, 2008
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star2you like it: star it!

Other project properties

Category:Uncategorized
Language:VHDL
Development status:
Additional info:
WishBone compliant: No
WishBone version: n/a
License:

Light Uart

This project contains a Basic and generic UART SerDes controller.

Features

Configuration:
-Enable/Disable Odd/Even parity bit
-bit stop number Enable/Disable
-baud rate selection
*1200
*2400
*4800
*9600
*19200
*38400
*57600
*115200
*230400
*460800
*921600

Note:
Br*br_divisor=921.600
Fclk/921.600=clk_divisor
=> Br=Fclk/(clk_divisor*br_divisor)=1/((clk_divisor*Tclk)*br_divisor)

Status

- TC