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Name: uriscv
Created: Jul 18, 2021
Updated: Jul 19, 2021
SVN Updated: Jul 19, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star0you like it: star it!

Other project properties

Category:Processor
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: Others

uriscv - Another tiny RISC-V implementation

Github: https://github.com/ultraembedded/core_uriscv

Simple, small, multi-cycle 32-bit RISC-V CPU implementation.
Most instructions take 2 cycles, apart from load/stores which take 4+ cycles (depending on memory latency), and division which can take up-to 34 cycles.

Features

  • 32-bit RISC-V ISA CPU core.
  • Support RISC-V’s integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).
  • Implements base ISA spec v2.1 and parts of the privileged ISA spec v1.11.
  • Supports machine mode privilege level only.
  • Configurable support for exceptions, interrupts, timers, multiplication, division and error traps.
  • Verified using random instruction sequences using cosimulation against C++ ISA model.
  • Synthesizable Verilog 2001, Verilator and FPGA friendly.
  • Coremark: 1.48 CoreMark/MHz (with HW mul/div)
  • Dhrystone: 0.58 DMIPS/MHz ('legal compile options' / 337 instructions per iteration / with HW mul/div)

For my higher performance pipelined cores, see here:

Getting Started

Cloning

To clone this project and its dependencies;

git clone https://github.com/ultraembedded/core_uriscv.git

Running Helloworld

To run a simple test image on the core RTL using Icarus Verilog;

# Install Icarus Verilog (Debian / Ubuntu / Linux Mint)
sudo apt-get install iverilog

# [or] Install Icarus Verilog (Redhat / Centos)
#sudo yum install iverilog

# Run a simple test image (test.elf)
cd tb/tb_core_icarus
make

The expected output is;

Starting bench
VCD info: dumpfile waveform.vcd opened for output.

Test:
1. Initialised data
2. Multiply
3. Divide
4. Shift left
5. Shift right
6. Shift right arithmetic
7. Signed comparision
8. Word access
9. Byte access
10. Comparision

Configuration

Param NameValid RangeDescription
SUPPORT_MUL1/0Enable multiplication instructions.
SUPPORT_DIV1/0Enable division instructions.
SUPPORT_CSR1/0Global enable for CSR/trap/interrupt handling.
SUPPORT_TRAP_LSU_ALIGN1/0Enable unaligned memory load / store exception.
SUPPORT_MTVEC1/0Configurable exception entry address.
SUPPORT_MTVAL1/0Support MTVAL CSR (holds bad addr / opcode).
SUPPORT_MIP_MIE1/0Support MIE and MIP CSR registers.
SUPPORT_MSCRATCH1/0Support MSCRATCH CSR registers (SW read/write).
SUPPORT_MCYCLE1/0Support cycle counter / rdtime.
SUPPORT_MTIMECMP1/0Non-std - support timer compare interrupt.
SUPPORT_TRAP_INVALID_OPC1/0Fault on invalid opcodes (enable SW emulation).
SUPPORT_BRAM_REGFILE1/0FPGA BlockRAM friendly reg file (inst take 1 cycle longer).
ISR_VECTOR'h0-FFFFFFFFISR addr = reset_vector + ISR_VECTOR (SUPPORT_MTVEC = 0).