The PCI Express end point core runs at 250 MHz, this clock is generated from a 100 MHz reference clock source from the connector fingers
!! clock stability is fundamental for PCI Express to work!!
Another user application clock needs to be provided for the register map synchronization stage
The example design has been created for the Virtex-7 FPGA VC709 Connectivity Kit, featuring a Xilinx XC7VX690T-2FFG1761C FPGA.
This FPGA is equipped with a PCI Express Gen3 hard block.
The design has been ported to: