WISHBONE DMA/Bridge IP Core

Current always statement reads in wb_dma_wb_mast.v reads:

always @(posedge clk) if(wb_ack_i) mast_dout <= #1 wb_data_i;

but this causes Xes to show up on wb0m_data_o which causes problems when connected to a wb2opb interface. Reseting the register avoids spurious Xes in simulation. To update is a requirement for using this IP core on an OPB bus.

always @(posedge clk or negedge rst) if(!rst) mast_dout <= 32'h00000000; else if(wb_ack_i) mast_dout <= #1 wb_data_i;