Usselmann, Rudolf

WISHBONE DMA/Bridge IP Core

The data vector pairs wb0s_data_ and wb0m_data_ are sorted to the wrong interface signal list, see my comments in original code section of file wb_dma_top.v:

// Slave Interface
input	[31:0]	wb0s_data_i; // wb0s_data_i belongs to WB master interface!
output	[31:0]	wb0s_data_o; // wb0s_data_i belongs to WB master interface!
input	[31:0]	wb0_addr_i;
input	[3:0]	wb0_sel_i;
input		wb0_we_i;
input		wb0_cyc_i;
input		wb0_stb_i;
output		wb0_ack_o;
output		wb0_err_o;
output		wb0_rty_o;

// Master Interface
input	[31:0]	wb0m_data_i; // wb0m_data_i belongs to WB slave interface!
output	[31:0]	wb0m_data_o; // wb0m_data_o belongs to WB slave interface!
output	[31:0]	wb0_addr_o;
output	[3:0]	wb0_sel_o;
output		wb0_we_o;
output		wb0_cyc_o;
output		wb0_stb_o;
input		wb0_ack_i;
input		wb0_err_i;
input		wb0_rty_i;

Mixup of master and slave data vectors

Current always statement reads in wb_dma_wb_mast.v reads:

always @(posedge clk)
        if(wb_ack_i)	mast_dout <= #1 wb_data_i;

but this causes Xes to show up on wb0m_data_o which causes problems when connected to a wb2opb interface.  Reseting the register avoids spurious Xes in simulation.  To update is a requirement for using this IP core on an OPB bus.

always @(posedge clk or negedge rst)
        if(!rst)        mast_dout <= 32'h00000000;
        else
        if(wb_ack_i)	mast_dout <= #1 wb_data_i;

Suggestion - initialize mast_dout in wb_dma_wb_mast.v block

I believe some tools will accept this however Xilinx's XST synthesizer 8.1.03i does not.   Request change on the following two always statements.

wb_dma_pri_enc_sub.v line 101 - remove parameter pri_sel from sensitivity list:

// Select Configured Priority
always @(pri_out_d0 or pri_out_d1 or  pri_out_d2)
	case(pri_sel)		// synopsys parallel_case full_case
	   2'd0: pri_out_d = pri_out_d0;
	   2'd1: pri_out_d = pri_out_d1;
	   2'd2: pri_out_d = pri_out_d2;
	endcase
// always @(pri_sel or pri_out_d0 or pri_out_d1 or  pri_out_d2)
// 	case(pri_sel)		// synopsys parallel_case full_case
// 	   2'd0: pri_out_d = pri_out_d0;
// 	   2'd1: pri_out_d = pri_out_d1;
// 	   2'd2: pri_out_d = pri_out_d2;
// 	endcase

II. wb_dma_ch_pri_enc.v - remove pri_sel from sensitivity list

// Select configured priority
always @(pri_out0 or pri_out1 or  pri_out2)
  begin
	case(pri_sel)		// synopsys parallel_case full_case
	   2'd0: pri_out = pri_out0;
	   2'd1: pri_out = pri_out1;
	   2'd2: pri_out = pri_out2;
	endcase // case(pri_sel)
    end
// // Select configured priority
// always @(pri_sel or pri_out0 or pri_out1 or  pri_out2)
// 	case(pri_sel)		// synopsys parallel_case full_case
// 	   2'd0: pri_out = pri_out0;
// 	   2'd1: pri_out = pri_out1;
// 	   2'd2: pri_out = pri_out2;
// 	endcase

Use of parameters in always sensitivity list fails in Xilinx XST 8.1.03i

Pg 26 of WISHBONE DMA/IP Bridge IP Core, dma_doc.pdf Rev 1.5, January 27,2002, section 4.4.4 indicates that the value after reset is FFFFFFFCh.  It should be FFFFFFF0h.

From wb_dma_ch_rf.v module,

assign ch_am0		= (CH_EN & HAVE_CBUF) ? {ch_am0_r, 4'h0}    : 32'hffff_fff0;

and ch_am0_r is defined:

always @(posedge clk or negedge rst)
	if(!rst)		ch_am0_r <= #1 28'hfffffff;
	else
	if(ch_am0_we)		ch_am0_r <= #1 wb_rf_din[31:4];

So the default value for ch_am0 is 32'hfffffff0;

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WISHBONE DMA/Bridge IP Core