OpenCores

WISHBONE DMA/Bridge IP Core :: Overview



Project maintainers

Details

Name: wb_dma
Created: Sep 25, 2001
Updated: Jun 10, 2018
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 5 reported / 0 solved
Star0you like it: star it!

Other project properties

Category:System on Chip
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License:

Description

This is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same interfaces.

Some of the main features are:
- Up to 31 DMA Channels
- 2, 4 or 8 priority levels
- Linked List Descriptors support
- Circular Buffer support
- FIFO buffer support
- Software & Hardware handshake support
- Automatic Channel Registers Reload support
- Fully configurable

Please see the spec for more details !

Status

- 8/2/2001 Added another feature: Now you can backoff to the beginning of the current transfers (this is useful for things like Etherenet, where you might have to restart in case of collisions or errors).
- New Directory Structure ! We have agreed on a common directory structure at OpenCores.
- I will post a message to cores@opencores.org each time I have an update

Change log

- 8/2/2001 Added another feature, Directory Structure has changed
- 6/6/2001 RU Second Release
- 19/3/2001 RU Released Code
- 16/3/2001 RU Initial web page

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