The data vector pairs wb0sdata and wb0mdata are sorted to the wrong interface signal list, see my comments in original code section of file wb_dma_top.v:
// Slave Interface input 31:0 wb0s_data_i; // wb0s_data_i belongs to WB master interface! output 31:0 wb0s_data_o; // wb0s_data_i belongs to WB master interface! input 31:0 wb0_addr_i; input 3:0 wb0_sel_i; input wb0_we_i; input wb0_cyc_i; input wb0_stb_i; output wb0_ack_o; output wb0_err_o; output wb0_rty_o;
// Master Interface input 31:0 wb0m_data_i; // wb0m_data_i belongs to WB slave interface! output 31:0 wb0m_data_o; // wb0m_data_o belongs to WB slave interface! output 31:0 wb0_addr_o; output 3:0 wb0_sel_o; output wb0_we_o; output wb0_cyc_o; output wb0_stb_o; input wb0_ack_i; input wb0_err_i; input wb0_rty_i;
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I would actually assume the mistake is made on file "wb_dma_wb_if.v". There, the connections are connected to the wrong cores:
wb_dma_wb_mast u0( .clk( clk ), .rst( rst ), .wb_data_i( wbs_data_i ), // IT SHOULD BE wbm_data_i .wb_data_o( wbs_data_o ), // IT SHOULD BE wbm_data_o .wb_addr_o( wb_addr_o ), .wb_sel_o( wb_sel_o ), .wb_we_o( wb_we_o ), .wb_cyc_o( wb_cyc_o ), .wb_stb_o( wb_stb_o ), .wb_ack_i( wb_ack_i ), .wb_err_i( wb_err_i ), .wb_rty_i( wb_rty_i ), .mast_go( mast_go ), .mast_we( mast_we ), .mast_adr( mast_adr ), .mast_din( mast_din ), .mast_dout( mast_dout ), .mast_err( mast_err ), .mast_drdy( mast_drdy ), .mast_wait( mast_wait ), .pt_sel( pt_sel_i ), .mast_pt_in( mast_pt_in ), .mast_pt_out( mast_pt_out ) );
wb_dma_wb_slv #(rf_addr) u1( .clk( clk ), .rst( rst ), .wb_data_i( wbm_data_i ), // IT SHOULD BE wbs_data_i .wb_data_o( wbm_data_o ), // IT SHOULD BE wbs_data_o .wb_addr_i( wb_addr_i ), .wb_sel_i( wb_sel_i ), .wb_we_i( wb_we_i ), .wb_cyc_i( wb_cyc_i ), .wb_stb_i( wb_stb_i ), .wb_ack_o( wb_ack_o ), .wb_err_o( wb_err_o ), .wb_rty_o( wb_rty_o ), .slv_adr( slv_adr ), .slv_din( slv_din ), .slv_dout( slv_dout ), .slv_re( slv_re ), .slv_we( slv_we ), .pt_sel( pt_sel_o ), .slv_pt_out( slv_pt_out ), .slv_pt_in( slv_pt_in ) );