tantos

WishboneTK toolkit

The component and entity declarations for the dpmem block do not match the port list used in the implementation in technology_behav.vhd.

When these are updated to match the architecture defined in technology_behav, it compiles fine. 

Shall I check in the fix or is someone working on this? It looks like someone was in the middle of something but the last check in was a while ago...

Doesn't compile - dpmem component & entity declarations don't match implementation

wb_bus_upsize.vhd
F: s_adr_o <= m_adr_i(m_adr_width-addr_diff downto addr_diff);
T: s_adr_o <= m_adr_i(m_adr_width-1 downto addr_diff);

wb_bus_upsize.vhd
F: wait on s_dat_i, m_adr_i;
T: --

*.vhd
F: little_endien
T: little_endian

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