WishboneTK toolkit

Description

WhisboneTK is a set of IP cores designed to be compatible with the Wishbone bus specification. The members of the tool-kit are general purpose building-blocks that (hopefuly) make designing Wishbone compatible devices easier. The elements in the libarary are avaliable free for any kind of use . The parts in the library use an extended signal-set than defined in the Wishbone interface. By moving all technology-specific code to a different, underlying package, the toolkit is fairly easy to port to other technologies. Currently Xilinx (XST) is the supported and tested platform though there's an Altera port included along with a generic behavioral description of all the technology-specific primitives that make sporting easy: Just make sure your implementation matches the behavioral model of the primities and the upper layer of modules should just work.

The elements currently in the library are:

• Output register
• Input register
• Two-way bus arbiter
• Asyncronous (SRAM-like) slave interface
• Asyncronous master interface
• Bus resizer
• Single-port RAM

There are some procedures useful for testing Wishbone devices in the package test.

Other elements planned for the toolkit:

• FIFO buffer
• Timer
• UART
• Dual-ported (shared) memory
• CACHE memory

Status

Currently in beta. Some of the cores are tested on real HW (x2s300e). Most cores are validated by simulation and all cores compile with XST 6.1.