Tanguay, Andre

Mahajan, Pratik

Ethernet 10GE MAC

I am creating a PlanAhead project (13.4) of this core. One of the features of the Xilinx ISE PlanAhead tool is that it has a hierarchical sources view. The header files, mainly define.v, are not imported as such, but I had to manually mark it as one.

Could the documentation reflect this?

Header Files Should be marked as such

Hi Andre ,

I've updated code for Verilator 3.813. The compilation errors still exist. I also found some other errors when simulating by modelsim. I would like to further discuss with you with email. mine is edwardliang668@gmail.com

Please reply me with email.

Updated code for Verilator 3.813.

./compile.sh errors found!

===================================================

../../../tbench/systemc/sc_main.cpp:149: error: no match for call to `(sc_core::sc_out<uint64_t>) (sc_core::sc_signal<sc_dt::sc_bv<64> >&)'
/usr/local/systemc-2.2/include/sysc/communication/sc_port.h:311: note: candidates are: void sc_core::sc_port_b<IF>::operator()(IF&) [with IF = sc_core::sc_signal_inout_if<uint64_t>]
/usr/local/systemc-2.2/include/sysc/communication/sc_port.h:320: note:                 void sc_core::sc_port_b<IF>::operator()(sc_core::sc_port_b<IF>&) [with IF = sc_core::sc_signal_inout_if<uint64_t>]
../../../tbench/systemc/sc_main.cpp:225: error: no matching function for call to `Vxge_mac::trace(SpTraceFile*&, int)'
./Vxge_mac.h:394: note: candidates are: void Vxge_mac::trace(VerilatedVcdC*, int, int)
make: *** [sc_main.o] Error 1
g++  -I.. -I. -I/usr/local/systemc-2.2/include -I/root/ethernet_10ge_mac/verilator/SystemPerl-1.337/src -I. -MMD -I/root/ethernet_10ge_mac/verilator/verilator-3.813/include -I/root/ethernet_10ge_mac/verilator/verilator-3.813/include/vltstd -DVL_PRINTF=printf -DVM_TRACE=1 -DVM_COVERAGE=0    -I/usr/local/systemc-2.2/include  -c -o verilated.o /root/ethernet_10ge_mac/verilator/verilator-3.813/include/verilated.cpp
make: *** No rule to make target `SpTraceVcd.o'.  Stop.
make: *** No rule to make target `SpTraceVcdC.o'.  Stop.
g++: sc_main.o: No such file or directory
g++: SpTraceVcdC.o: No such file or directory
g++: SpTraceVcd.o: No such file or directory

compile errors found!

./compile.h errors found!!!
==============================================


../../../tbench/systemc/sc_main.cpp:149: error: no match for call to `(sc_core::sc_out<uint64_t>) (sc_core::sc_signal<sc_dt::sc_bv<64> >&)'
/usr/local/systemc-2.2/include/sysc/communication/sc_port.h:311: note: candidates are: void sc_core::sc_port_b<IF>::operator()(IF&) [with IF = sc_core::sc_signal_inout_if<uint64_t>]
/usr/local/systemc-2.2/include/sysc/communication/sc_port.h:320: note:                 void sc_core::sc_port_b<IF>::operator()(sc_core::sc_port_b<IF>&) [with IF = sc_core::sc_signal_inout_if<uint64_t>]
../../../tbench/systemc/sc_main.cpp:225: error: no matching function for call to `Vxge_mac::trace(SpTraceFile*&, int)'
./Vxge_mac.h:394: note: candidates are: void Vxge_mac::trace(VerilatedVcdC*, int, int)
make: *** [sc_main.o] Error 1
g++  -I.. -I. -I/usr/local/systemc-2.2/include -I/root/ethernet_10ge_mac/verilator/SystemPerl-1.337/src -I. -MMD -I/root/ethernet_10ge_mac/verilator/verilator-3.813/include -I/root/ethernet_10ge_mac/verilator/verilator-3.813/include/vltstd -DVL_PRINTF=printf -DVM_TRACE=1 -DVM_COVERAGE=0    -I/usr/local/systemc-2.2/include  -c -o verilated.o /root/ethernet_10ge_mac/verilator/verilator-3.813/include/verilated.cpp
make: *** No rule to make target `SpTraceVcd.o'.  Stop.
make: *** No rule to make target `SpTraceVcdC.o'.  Stop.
g++: sc_main.o: No such file or directory
g++: SpTraceVcdC.o: No such file or directory
g++: SpTraceVcd.o: No such file or directory

Untitled bug

The generic_fifo_ctrl module synchronizes gray representation of the read and write pointers. The gray representation is coming from combinational bin2gray function instead of DFF output.

This method may generate a static hazard that gets synchronized by the other clock domain and violates the gray pointer principle of single bit flip.

For safe coding the gray representation on the source clock domain should be sampled. To get cycle accurate behavior of the original design sample the bin2gray conversion of the next binary pointer value in parallel to sampling the binary pointer itself.

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Ethernet 10GE MAC