YACC-Yet Another CPU CPU

Description

YACC (Yet Another CPU CPU) is MIPS I (TM) subset cpu written in Verilog-2001 HDL. YACC has 5 pipeline and shows 110 DMIPS in stratix2 with synthesized allowable clock of 165MHz. It is independent design of plasma, although YACC uses gcc-elf-mips tools provided by Steve Rhords, author of plasma (Most mips written in VHDL).
The core was developed by using my Simulator, with post layout gate simulation, and tested by actual FPGAs, using Xilinx spartan3 starter kit and Cyclone by Altera,running 800 digits of pi calculation ,(255,223) Reed Solomon Error Correction ,and Interactive calculator written by C language.

Disclaimer

MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS Technologies, Inc. MIPS Technologies, Inc. does not endorse and is not associated with this project. Tak.Sugawara is not affiliated in any way with MIPS Technologies, Inc.

Legal

I have no idea if implementing this core will or will not violate
patents, copyrights or cause any other type of lawsuits.

I provide this core "as is", without any warranties. If you decide to
build this core, you are responsible for any legal resolutions, such
as patents and copyrights, and perhaps others ....

THIS SOURCE FILE(S) IS/ARE PROVIDED "AS IS" AND WITHOUT ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.

Background

When I was developing VHDL to Verilog translator , I found plasma core in opencores. It is excellent work to learn a lot. After I translated plasma written by VHDL to Verilog HDL almost automatically using my Translator, I stated to design my own CPU per following target spec.

-works with free C compiler ->use plasma resources
-pretend to be fast (Dhrystone benchmark test requires only 16KB memory! Actually ..)
-5 stage pipeline
-use dual port memory in FPGA
-works with Altera/Xilinx FPGAs
-with minimum logic cells in FPGA