YiFive (A Risc-v based SOC)
Project maintainers
Details
Name: yifive
Created: Dec 13, 2020
Updated: Dec 13, 2020
SVN Updated: Jun 13, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Dec 13, 2020
Updated: Dec 13, 2020
SVN Updated: Jun 13, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star0you like it: star it!
Other project properties
Category:System on Chip
Language:Verilog
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
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The url of the svn repository is: https://opencores.org/websvn/listing/yifive/yifive
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