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Pipelined DCT/IDCT :: Overview

Details

Name: dct_idct
Created: Feb 1, 2010
Updated: Oct 10, 2012
SVN Updated: Feb 2, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved

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Other project properties

Category: DSP core
Language: VHDL
Development status: Stable
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

DCT soft core is the unit to perform the Discrete Cosine Transform (DCT). It performs twodimensional 8 by 8 point DCT for the period of 64 clock cycles in pipelined mode.

Main Features:

  • more than 300 MHz sampling frequency, 64-cycle calculation period,
  • approximately 330 CLBs and 4 DSP48E in Virtex-5 device,
  • 2 DSP48E when the scaled output data mode is used,
  • 8-bit input data,
  • 11-bit coefficients,
  • 12 – bit results,
  • pipelined mode,
  • latent delay from input to output is 132 clock cycles,
  • structure optimized for Xilinx Virtex, Spartan FPGA devices.

Please, contact us if you wish to have this IP core modified or adjusted to meet your requirements.

This core is provided by Unicore Systems http://unicore.co.ua. To view our product list of commercial IP cores, please, follow this link

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