or1200_soc :: Overview

Project maintainers


Name: or1200_soc
Created: Mar 16, 2009
Updated: Feb 27, 2010
SVN Updated: Mar 29, 2011
SVN: Browse
Latest version: download
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Other project properties

Category: System on Chip
Language: Verilog
Development status: Beta
Additional info: FPGA proven
WishBone compliant: Yes
WishBone version: n/a


This project is an example of using OpenRISC on an Terasic DE1 development board. UBoot has been ported. The old ecos 2.0 has been ported to ecos 3.0. The adv_debug_sys unit was integrated but not tested.

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