or1200_soc
Project maintainers
Details
Name: or1200_soc
Created: Mar 16, 2009
Updated: Apr 4, 2018
SVN Updated: Mar 29, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Created: Mar 16, 2009
Updated: Apr 4, 2018
SVN Updated: Mar 29, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved
Star1you like it: star it!
Other project properties
Category:System on Chip
Language:Verilog
Development status:Beta
Additional info:FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License:
Language:Verilog
Development status:Beta
Additional info:FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License:
Overview
This project is an example of using OpenRISC on an Terasic DE1 development board. UBoot has been ported. The old ecos 2.0 has been ported to ecos 3.0. The adv_debug_sys unit was integrated but not tested.
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