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Reed-Solomon Codec Generator :: Overview

Project maintainers

Details

Name: reed_solomon_codec_generator
Created: Jul 21, 2011
Updated: Jan 19, 2017
SVN Updated: Jul 28, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 2 reported / 0 solved

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Other project properties

Category: ECC core
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This tool working on WinXP is used to generate verilog-RTL for Reed-Solomon Codec.
- Selectable Decoder/Encoder/Both
- Symbol width 3,4,5,6,7,8,9,10,11
- Primitive polynomial
- Erasure Enable/Disable
- Configurable Data I/F
- Automatically available testbench
- Distributed under the GPL license

If you need more customize or hi-performance IP, please let us know.
info@syslsi.com

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