Another SPI Controller (with FIFO) :: Overview

Project maintainers


Name: spi_master_controller
Created: Mar 12, 2015
Updated: Jun 20, 2017
SVN: No files checked in

Other project properties

Category: Communication controller
Language: VHDL
Development status: Stable
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL


This is a simple SPI Master Core with a FIFO buffer. It was created following this timing diagram SPI Timing diagram


Until I figure out how to upload the file to the OpenCores SVN Server, the files will be available to download on my github repository here

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