Rosales, Diego

Another SPI Controller (with FIFO)

## Description

This is a simple SPI Master Core with a FIFO buffer. It was created following this timing diagram ![SPI Timing diagram](/usercontent/img/1426525700)

## Download

Until I figure out how to upload the file to the OpenCores SVN Server, the files will be available to download on my github repository here [https://github.com/DiegoRosales/VHDL\_Modules/tree/master](https://github.com/DiegoRosales/VHDL_Modules/tree/master)SPI


<h2 id="description">Description</h2>
<p>This is a simple SPI Master Core with a FIFO buffer. It was created following this timing diagram
<img src="/usercontent/img/1426525700" alt="SPI Timing diagram" />
</p>
<h2 id="download">Download</h2>
<p>Until I figure out how to upload the file to the OpenCores SVN Server, the files will be available to download on my github repository here <a href="https://github.com/DiegoRosales/VHDL_Modules/tree/master" target="_blank">https://github.com/DiegoRosales/VHDL_Modules/tree/master</a>SPI</p>


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Another SPI Controller (with FIFO)

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