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Attiny Atmega Xmega core :: Overview

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Details

Name: attiny_atmega_xmega_core
Created: Mar 18, 2018
Updated: Sep 13, 2018
SVN: No files checked in
Bugs: 1 reported / 0 solved

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Other project properties

Category: Processor
Language: Verilog
Development status: Beta
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This is a configurable Atmel processor and support eight configurations:
1) REDUCED
2) MINIMAL
3) CLASSIC_8K
4) CLASSIC_128K
5) ENHANCED_8K
6) ENHANCED_128K
7) ENHANCED_4M (Not supported yet)
8) XMEGA

I provide the links directly to GIT projects for easy update.

The processor IP and several IO IP's and can be downloaded from here: https://git.morgothdisk.com/VERILOG/VERILOG-UTIL-IP/tree/master/xmega_core

The implementation example will oscillate between DIGILENT Arty and NexusVideo depending where I am when I make the last update and can be downloaded from here: https://git.morgothdisk.com/VERILOG/VERILOG-XMEGA-CORE-IP-TST

On this directory, under the AtmelStudio project example debug directory's is an application that help developers to easy convert .hex files to .mem files and is described here: https://git.morgothdisk.com/VERILOG/INTEL-HEX-TO-VERILOG-MEM

The implementation for LATTICE MachXOFL Starter Kit can be downloaded from here: https://git.morgothdisk.com/VERILOG/VERILOG-XMEGA-CORE-IP-TST-LATTICE

On LATTICE platforms it seems that Latice Diamond have some issues with generic distributed BRAM RAM's and ROM's, until Lattice will give a workaround for this issue without using IPxpress.

All details about this core on GIT

I begin to add support for this core on CPP-SDK that can be found here: https://git.morgothdisk.com/C-CPP/MULTIPLATFORM-CPP-SDK/tree/master/ExampleXmega_FPGA

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