TV80 :: Overview


Name: tv80
Created: May 14, 2004
Updated: Nov 13, 2015
SVN Updated: Feb 2, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 9 reported / 7 solved

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Other project properties

Category: Processor
Language: Verilog
Development status: Mature
Additional info: ASIC proven, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: BSD


The TV80 is an 8-bit Z80-compatible microprocessor core, written in Verilog. It is based on Daniel Wallner's VHDL T80 core.


- executes 8080/Z80 instruction set
- cycle timing is similar to original Z80
- small die area
- sample peripheral with GMII interface
- Optional Wishbone wrapper for TV80 core now available


- taped out in TSMC 130nm (250 Mhz, ~20k gates)
- taped out in TSMC 65nm process (125 Mhz)
- Microprocessor-controlled verification environment

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